
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.std_logic_textio.all;

USE work.types.all;
USE work.mem_file.all;

ENTITY ram IS
    PORT
    (
        address  : IN   MEMADDR;
        clock    : IN   STD_LOGIC  := '1';
        data     : IN   MEMDATA;
        wren     : IN   STD_LOGIC;
        q        : OUT  MEMDATA
    );
END ram;


ARCHITECTURE sync OF ram IS
    SIGNAL word_list    : word_array := READ_MEMORY_FILE("dmemory.txt");
--    SIGNAL address_aux  : MEMADDR   := (OTHERS => '0');
BEGIN


    PROCESS (clock)
    BEGIN
        IF rising_edge(clock) THEN
--            address_aux <= address;
            
            q <= word_list( CONV_INTEGER( address ) ) &
                 word_list( CONV_INTEGER( address )+1 ) &
                 word_list( CONV_INTEGER( address )+2 ) &
                 word_list( CONV_INTEGER( address )+3 );
            IF wren = '1' THEN
                word_list( CONV_INTEGER( address )+0 ) <= data(31 downto 24);
                word_list( CONV_INTEGER( address )+1 ) <= data(23 downto 16);
                word_list( CONV_INTEGER( address )+2 ) <= data(15 downto 8 );
                word_list( CONV_INTEGER( address )+3 ) <= data(7  downto 0 );
            END IF;
        END IF;
    END PROCESS;
END sync;
